The present invention relates generally to memory systems. More specifically, the invention provides a hard-IP memory controller and a soft-IP frequency converter. Merely by way of example, the invention has been applied to a fully buffered DIMM system and method, but it would be recognized that the invention has a much broader range of applicability.
The fully buffered DIMM technology often uses two signal interfaces between memory controller and memory chips. One interface is between the memory chips and a buffer, and the other interface is between the buffer and the memory controller. The buffer is often an advanced memory buffer (AMB). For example, the interface between the memory chips and the AMB can support the double data rate. In another example, the interface between the AMB and memory controller is a serial interface.
A conventional fully buffered DIMM memory system includes memory chips, advanced memory buffers, a memory controller, a physical media attachment (PMA) electrical interface and physical coding sub-layer (PCS), and a controller configuration system. These components can be implemented in field programmable gate arrays (FPGAs) to support high-throughput IP protocols. But the implementation often uses a large number of programmable logic elements, and therefore can be very expensive. As a result, users often port these components to application-specific integrated circuits (ASICs) in order to reduce system costs. But this cost reduction comes at the expense of programmability. Hence it is desirable to improve techniques for memory systems.